Due to continuing technological innovations in the field of semiconductor fabrication, IC (integrated circuit) manufactures are developing ICs with larger scale of integration, higher device density, lower power consumption and higher operating speeds. Typically, highly integrated circuits are designed using multi-level interconnection structures that include intra-level interconnects (metal lines/wiring) and inter-level interconnects (plugs/contacts) embedded in interlayer dielectric (ILD) material, which are formed from different metal layers as part of a BEOL (back end of line) metallization process. Contact plugs are also formed to connect active devices in a silicon wafer to a first level of metallization.
Various methods have been developed to form interconnection structures. For instance, FIG. 1 schematically illustrates a conventional interconnection structure. More specifically, FIG. 1 schematically illustrates a semiconductor device (10) having a conventional bi-metal interconnection structure in which different conductive materials are used to form contact plugs and metal lines. Referring to FIG. 1, the semiconductor device (10) comprises a semiconductor substrate (11) having an active device (12) formed thereon. The active device (12) (e.g., MOS transistor) comprises a polysilicon gate structure (12a) and source/drain diffusion regions (12b, 12c).
A plurality of ILD (interlayer dielectric) layers (13), (14) and (15) are formed over the substrate (11). A first ILD layer (13) is formed to cover the active device (12). A plurality of plugs (16) are formed in the ILD layer (13) to provide contacts between gate (12a) and source/drain regions (12b, 12c) and respective metal wiring/pads (17) (i.e., metallization level M1) that are embedded in the second ILD layer (14). A plurality of plugs (18) are formed in the ILD layer (14) to provide contacts between the metal wiring/pads (17) and respective metal wiring/pads (19) (i.e., metallization level M2) that are embedded in the third ILD layer (15). A plurality of plugs (20) are formed in the ILD layer (15) to provide contacts between the metal wiring/pads (19) and wiring/pads of a next metallization level.
In the conventional embodiment of FIG. 1, the plugs (16, 18, 20) and metal wiring/pads (17, 19) are formed from different conductive materials. For instance, a refractory metal such as tungsten (W) is typically used to form the contact plugs. The metal wiring/pads (17) and (19) can be formed using aluminum or copper or alloys thereof. Different methods may be used to construct interconnect structures depending on the wiring material.
For example, a subtractive metal etch process is commonly used when the metal wiring/pads are formed using Al, for example. With such method, the interconnect structure of FIG. 1 could be formed as follows. The ILD layer (13) (e.g., silicon dioxide) is deposited and a photolithographic process is performed to form via hole openings in the ILD layer (13). A liner/barrier material is deposited to line the via holes and a layer of tungsten is deposited to fill the via holes. Excess tungsten material is removed by chemical mechanical polishing (CMP) to make the top surface of the plugs (16) coplanar with the top surface of the ILD layer (13).
The metallization layer M1 is then formed by depositing and etching a layer of Al using well-known techniques to form the wiring/pad pattern. After M1 is formed, a layer of dielectric material is deposited and planarized to form the second ILD layer (14). Thereafter, the contact plugs (18) of the second ILD layer (14) are formed using a photolithographic process to form via hole openings in the ILD layer (14) down to respective wires/pads (17), depositing a liner/barrier material and a layer of tungsten to fill the via holes, and then removing excess tungsten material by chemical mechanical polishing (CMP) to make the top surface of the plugs (18) coplanar with the top surface of the ILD layer (14). The second level metallization M2 wires/pads (19), ILD layer (15) and plugs (20) (as well as upper layers) are formed by repeating this process.
On the other hand, when copper Cu is used to form the wiring/pads (17) and (19), a subtractive etch process is not typically used because copper is difficult to pattern using a conventional photolithography/etching techniques, especially when the copper wires are formed according to relatively small design rules. Instead, the interconnect structure of FIG. 1 can be formed using a conventional single damascene process, as follows. The ILD layer (13) (e.g., silicon dioxide) is deposited and a photolithographic process is performed to form via hole openings in the ILD layer (13). A liner/barrier material is deposited to line the via holes and a layer of tungsten is deposited to fill the via holes. Excess tungsten material is removed by chemical mechanical polishing (CMP) to make the top surface of the plugs (16) coplanar with the top surface of the ILD layer (13). Next, a dielectric layer is deposited and trench openings are formed in the dielectric layer aligned to the plugs (16).
A liner (or diffusion barrier) material is deposited to line the trenches and a layer of copper is deposited to fill the trenches using known techniques (e.g., electroplating). Typically, Ti/TiN is utilized as the liner material for tungsten and Ta/TaN is utilized as the liner material for copper. Thereafter, excess copper material is removed by chemical mechanical polishing (CMP) to make the top surface of the metal wires/pads (17) coplanar with the top surface of the dielectric layer.
Next, a capping layer (such as SiN or SiCN) and a second dielectric layer are sequentially deposited over the planarized dielectric layer including wires/pads (17). A capping layer is typically deposited before the second dielectric layer to thereby protect the copper material from oxidation during deposition of the second dielectric layer. Via openings are then formed in the second dielectric layer down to the wires/pads (17). Next, a liner material is deposited to line the via holes and a layer of tungsten is deposited to fill the via holes. Excess tungsten material is removed by chemical mechanical polishing (CMP) to make the top surface of the plugs (18) coplanar with the top surface of the second dielectric layer. With this method, the ILD layer (14) is formed by two separate layers of dielectric (via-level and line-level). The above process is repeated for each subsequent metal-plug level.
With each of the conventional methods discussed above, a CMP process is performed after deposition of the plug material (tungsten) to remove the excess material and planarize the surface of ILD layers and plugs. In general, CMP has proven to be problematic in this regard, causing interconnect defects and anomalies that reduce final chip yield. For example, CMP can result in what is known as “dishing” due to variation in hardness of materials being chemically/mechanically polished. For instance, oxide material that is used to form the ILD layers is harder than copper or aluminum. Consequently, CMP can cause dishing metal interconnects, which can thin the wire or pad and result in higher-resistance wires or lower-reliability bond pads.
Moreover, CMP can result in what is known as “erosion”, where the conductive material and ILD are both removed at a faster rate in one area of the wafer than at other areas. Erosion typically occurs in dense pattern areas of the wafer. For instance, FIG. 2 schematically illustrates erosion resulting from CMP. FIG. 2 illustrates an ILD layer (25) having a dense pattern of plugs (26). In FIG. 2, erosion results in a sub-planar dipping surface (25b) below the surrounding planar surface regions (25a). The erosion can cause short circuits between adjacent wires on the next layer.
FIG. 3 schematically illustrates another conventional interconnection structure. More specifically, FIG. 3 schematically illustrates a semiconductor device (30) having a conventional interconnection structure which is formed, in part, using a “dual damascene” process, which eliminates a CMP step after plug metal deposition. Referring to FIG. 3, the semiconductor device (30) comprises a semiconductor substrate (31) having an active device (32) formed thereon. The active device (32) (e.g., MOS transistor) comprises a polysilicon gate structure (32a) and source/drain diffusion regions (32b, 32c). A plurality of ILD (interlayer dielectric) layers (33), (34) and (35) are formed over the substrate (31). A first ILD layer (33) is formed to cover the active device (32). A plurality of plugs (36) are formed in the ILD layer (33) to provide contacts between gate (32a) and source/drain regions (32b, 32c) and respective metal wiring/pads (37) (i.e., metallization level M1) that are embedded in the second ILD layer (34). Assuming the wiring/pads (37) are formed of copper and the plugs (36) are formed of tungsten, these structures can be formed using conventional methods discussed above with reference to FIG. 1.
The third ILD layer (35) includes a plurality of plugs (38) and respective metal wiring/pads (39) (i.e., metallization level M2) that are formed of copper using a “dual damascene” process. In general, a dual damascene process includes forming a via hole and a trench region in an interlayer dielectric (ILD) layer in alignment with a predetermined region of a lower metal line. The via hole and trench region are then filled with copper material in a single copper deposition process (e.g., electroplating) to integrally form the metal lines (39) and respective contacts (38).
In a dual-damascene (DD) structure, only a single metal deposition step is used to simultaneously form the main metal lines and the metal in the vias. That is, both trenches and vias are formed in a single dielectric layer. In contrast to the methods for forming bi-metal interconnect structures as discussed above with reference to FIG. 1, the dual damascene process forms an integrated wire/plug structure at each level, thereby reducing or otherwise eliminating potential defects that can occur between plugs and metal layers due to erosion from the CMP.
Although dual damascene methods allow formation of metal interconnect structures that yield improved performance, such methods become more problematic with decreasing design rules. For example, as the pitch between interconnection lines is decreased to meet smaller design rule requirements, the critical dimensions of the metal wiring become more narrow and the aspect ratio of the contact holes for electrically connecting upper and lower metal wiring is increased. It is difficult to sufficiently fill high aspect ratio holes and vias with copper using current technology. Moreover, the use of copper to form contacts between the active semiconductor devices and the first level metallization M1 is problematic with regard to copper diffusion into the silicon.